Intel has announced a number of major new initiatives for the design and manufacturing of future CPUs and GPUs. The company revealed new roadmaps and details of the technology that will underpin future products, and even demonstrated some prototypes in action, at its Architecture Day seminar on Tuesday at the former home of Intel co-founder Robert Noyce in Los Altos, California. According to Intel’s Core and Visual Computing Group senior vice-president Raja Koduri, “We operate in a world where we generate data at a faster rate than our ability to analyze, understand and help secure it… We have a bold engineering vision over the next five years to deliver 10 petaflops of compute and 10 petabytes of data within 10 milliseconds to every person in the world.”
Central to Intel’s strategy going forward will be a new 3D stacked processor packaging technique that the company is calling Foveros, and the adoption of a chiplet-based topography allowing different blocks of logic to be manufactured separately and even using different process nodes.
According to Intel, Foveros will be the first time that 3D stacking will be used for high-performance logic such as a CPU or GPU. The first products built this way will be released in late 2019 and will leverage Intel’s upcoming 10nm CPU architecture on a 14nm base die that is likely to include memory control and power management functions. The chiplet approach will allow for the separate design and manufacturing of various logic blocks that can then be assembled using Foveros. This is somewhat similar to what AMD recently disclosed it was working on for future CPUs based on its Zen 2 architecture.
The next generation of Intel Core and Intel Xeon CPUs will have a significantly different architecture to the current lineup, which are all derived from the Skylake design. Codenamed ‘Sunny Cove’, Intel is touting improved instructions per clock as well as power efficiency. Sunny Cove will also introduce new extensions aimed at accelerating specific workloads including cryptography and AI.
On the integrated graphics front, Intel is skipping the Gen10 iGPU that was supposed to debut with the much-delayed 10nm Cannonlake CPUs. Instead, Gen11 will be integrated into undisclosed 10nm CPUs in 2019. Spearheaded by Raja Koduri’s new Core and Visual Computing team, the Gen11 iGPU promises to deliver performance of over 1 Teraflop and support high-quality current-day games. Perhaps the most interesting aspect of it will be support for Intel Adaptive Sync technology, an implementation of the VESA adaptive sync standard similar to (and potentially interoperable with) AMD’s Freesync. Intel also spoke about its upcoming discrete GPUs, which are targeted for a 2020 launch.
Intel was one of the first companies to launch QLC (quad-level cell) flash memory for SSDs and will be positioning its QLC offerings together with Optane SSDs as a very fast tiered storage solution. The company also talked about its Optane DC Persistent Memory for datacentres, promising responsiveness and latency at DRAM speeds, which could greatly accelerate large databases and AI workloads.
Finally, Intel covered its software efforts including a new “One API” stack to simplify the development of software that addresses CPUs and GPUs as well as FPGA chips and dedicated single-purpose accelerators. Another project is the Deep Learning Reference Stack, an open-source resource release for AI developers using Intel Xeon Scalable processors.
Anandtech, which was present at the event, also reported that Intel discussed a new ‘Xe’ brand for its graphics processors in 2020, which will span everything from integrated entry-level graphics to units optimised for gaming and data centre workloads. There are also details of an experimental Foveros-based hybrid X86 CPU that would combine Sunny Cove as well as Atom cores in a configuration similar to ARM’s big.Little designs. Such a chip would not only be physically tiny, but would have extremely low standby power consumption and would run without a fan.